Scientific leaders: Dr. Olivier TEMAM (Inria); Dr. Chengyong WU (ICT)
LIAMA founding members involved: Inria (France)
LIAMA associated members involved: ICT (China)
Other partners: EPFL
Creation: December 2011
The general goal of the research project is to propose a path forward for high-performance and embedded computing systems, compatible with the evolution of technology.For several decades, it was possible to translate transistor size reduction into faster performing processors. Some additional architecture complexity was involved at each generation, but essentially, programs run on a given processor would run faster on the next-generation processor without modification. Due to power constraints, this evolution has considerably slowed down since 2005, leading to multi-core architectures (several processors on the same chip), and raising severe programming (parallelization) challenges.Even more recently, in 2009, and again due to power constraints (Dark Silicon), the multi-core option itself is now being challenged. Because of these power constraints, all transistors on a chip can no longer be used simultaneously. As a result, cramming tens or hundreds of cores on a chip is not a viable option, as it will not be possible to use all these cores simultaneously. Consequently,the main option which is emerging, both for embedded and general-purpose computing systems,are heterogeneous multi-cores, a combination of cores and accelerators, where accelerators can be either very specialized circuits performing a single task, or more flexible circuits performing a broader range of tasks; examples of accelerators are ASICs (Application Specific Integrated Circuits), reconfigurable circuits, or GPUs (Graphics Processing Units). Heterogeneous multicores are not a new notion, they are widespread in embedded systems where they are known as SoCs (System-on-Chips). The challenge is to learn to use such heterogeneous multi-cores for general-purpose computing systems.
The two main goals of our research is the design and programming of heterogeneous multi-cores.The design part will focus on finding accelerators which can be high-performance and energyefficient,yet have a broad application scope. The programming part will focus on a programming approach which can make a program both efficient and seamlessly portable across accelerators, as one of the key programming challenges for accelerators is their varied and changing nature.